Learning goals#

  • Know how to install relevant tools

  • Apply the tools on an introductory task (e.g., programming)

Introductory problem#

The following code prints on the console in Python:


Hardware description languages (HDL) are used for designing digital circuits. A popular HDL is SystemVerilog (SV). Look at the following code:

module m;

initial begin
    $display("hello world");

  1. Guess what the code does.

  2. Does this code describe hardware?

    • If yes, how could a print statement behave in a digital system?

    • If no, what could be the purpose of such a statement?


Get access to the following tools (either local installation or remote):

  1. Verilator

  2. ccache to speed up the simulation binary generation in Verilator.

    After installation you can permanently enable ccache by using the following line for example:

    echo 'PATH="/usr/lib/ccache/bin:$PATH"' >> ~/.bashrc

    The line above ensures that the cached version of the C/C++ compiler is run instead of the normal one. The ccache path above (/usr/lib/ccache/bin) may be different in other Linux distributions. You also have to change ~/.bashrc if you use another shell than bash.

  3. Surfer

  4. verilator-makefile

  5. Vivado β€” Installation offers you some options. Selecting the following options is enough for this course:

    • Edition: Vivado ML Standard

    • Product: Vivado

    • Device support:

      • Zynq-7000 for high-level synthesis (HLS) related content

      • 7-Series for the rest of the content

      You find the installation configuration file that has these options set here: vivado-2023.2-install-config.txt. Instead of clicking the options yourself, you can also use:

      ./xsetup \
          --batch Install \
          --config vivado-*-install-config.txt \
          --agree XilinxEULA,3rdPartyEULA

    Warning for Linux: After installation make sure that you make the Vivado executables available in your PATH and set other tool related environment variables. Put source /opt/Xilinx/Vivado/*/ in your terminal emulator initialization file, e.g., ~/.bashrc like this:

    echo "source /opt/Xilinx/Vivado/*/" >> ~/.bashrc

    You may have to log out & log in so that this setting is also available to GUI programs.

    Alternatively you can execute the source command before you start working with the tools. For example the SystemVerilog plugin in Code editor requires xvlog command to be available in the PATH.

  6. vivado-makefile


# What is Verilator primarily used for? - [ ] Programming CPUs - [ ] Simulating C++ programs - [x] Simulating FPGA designs - [ ] Programming FPGAs # What is GTKWave used for? - [ ] Simulating C++ programs - [ ] Simulating FPGA designs - [x] Visualizing waveforms created by a simulation - [ ] Executing simulations # What is Vivado used for? - [ ] Simulating C++ programs - [x] Creating FPGA designs - [x] Simulating FPGA designs - [x] Programming FPGAs # What is makefile used for? - [ ] Simulating C++ programs - [x] For creating files based on rules and dependencies - [ ] Visualizing waveforms created by a simulation - [ ] Simulating FPGA designs

πŸŽ‰ Congratulations, now you are almost ready for the class. Please submit your questions from the preparation to your facilitator. Some prompts you want to consider:

  • Why do we have to work with makefiles?

  • Why do we need Verilator and a waveform viewer besides Vivado?

  • What is the best way to learn SV without installing any tools?

  • Why do we start to FPGA programming with tools?


Verilator & waveform viewer#

Verilator workflow


Vivado workflow


VS Code with

Configuring SV support plugin#

We will use

  • Verible as formatter, language server.

  • Verilator as linter.

After installing the plugin, go to the configuration page, and configure the following:

  1. Verilog > Language Server > Verible Verilog ls is active.

  2. Verilog > Linting: Linter is set to verilator.

  3. Verilog > Linting: Verilator: Arguments is set to --timing

Configuring autoformatting#

A properly formatted code is easier to read both for you and others. verible contains an autoformatter. Autoformatting your code on save:

  1. Go to the the settings. You find it on the left below represented with the gear βš™οΈ icon.

  2. Search for format on save

  3. Activate it.

You can also manually autoformat your file using CTRLShiftI.

Resulting settings.json#

Code configuration can also be done via settings.json.

Ctrlp opens the quick open palette. Write settings.json and press Enter. It should contain the following after the configuration in previous sections.

    "verilog.languageServer.veribleVerilogLs.enabled": true,
    "verilog.linting.linter": "verilator",
    "[systemverilog]": {
        "editor.defaultFormatter": "mshr-h.veriloghdl"
    "editor.formatOnSave": true,
    "verilog.linting.verilator.arguments": "--timing",

Testing the plugin#

First create a new file, e.g.,

Language server#

Start writing module in the editor. Then you should see a code completion window that contains keywords similar to:

module   module with parameters
module # module without parameters

Copy & paste the following code that has a wrong syntax.

module m

Then save it. Otherwise the linter may not be run.

You should see a waved red line under endmodule. When you hover over the waved red line, then you should see a message from Verilator similar to:

syntax error, ... verilator(verilator)

Copy & paste the following unformatted code.

module m;endmodule

Then Ctrls. After saving the code should look like this:

module m;

Example workflow in the Editor#

TODO, make -> waveform viewer loop


The language server and linter give you immediate feedback so that you can catch obvious errors before simulation or synthesis. In this chapter we setup these tools for a fast development write code -> verify loop.