An overview of processors#

We can use digital circuits for solving various digital design problems. A well-known example is the central processing unit (CPU) typically implemented as a microprocessor. However there are also other kinds of processors which may solve your problem at a lower cost, higher reliability, less energy consumption etc.

Learning goals#

  • Apply various processor types to a given problem scenario

Introductory problem#

You are working as an hardware engineer as part of an space avionics group that builds a data handling subsystem:

A satellite data handling subsystem connected to other subsystems

The fault-tolerant processor is a microprocessor and you are responsible for the FPGA design.

You are given the following task: The operating system running on the microprocessor has to write logging data to a large array of radiation-tolerant flash memory chips. The microprocessor does not have enough pins, so the flash memory chips are interfaced by the FPGA.

The microprocessor-FPGA link is based on a packet-based communication, where the packets are buffered in a FIFO with the following interface:

  • clk, clock

  • data, 1 byte

  • read_enable, 1 bit: Reads one data word of the packets sent by the microprocessor in every clk cycle

The write packet has the following structure:

  • address, 1 byte

  • length, 1 byte

  • payload, 0-255 bytes

The flash interface has the following interface:

  • clk

  • address, 1 byte

  • data, 1 byte

  • write_enable, 1 bit

Sketch an architecture for the hardware design on the FPGA by answering the following questions:

  1. What are the inputs and outputs of your design?

  2. How does the architecture of your design look like? Would you call your design a processor?

  3. Is your design programmable?

Optional: Implement a sketch of your design in HDL.

Tasks#

Read chapter 4: The variety of processors and computational engines, ch4, Comer, 2017.

Quiz#

<!-- processor architectures --> # Which of the following is NOT a characteristic of the Harvard Architecture as depicted in the reading? - [ ] It uses two separate memories, one for instructions and one for data. - [x] It allows the instruction memory to be used for storing data. - [ ] It is sometimes used in small embedded systems. > Refer to the section 4.3 in the book # Which category of processor is described as having the ability to change the sequence of steps each time it is invoked? - [ ] Fixed logic processor - [ ] Selectable logic processor - [ ] Parameterized logic processor - [x] Programmable logic processor # In a conventional processor, which component is responsible for overall program execution? - [ ] Arithmetic Logic Unit (ALU) - [ ] Local data storage - [x] Controller - [ ] External interface # What is a coprocessor? - [ ] A processor that operates independently of any other processor. - [x] A processor that operates in conjunction with and under the control of another processor. - [ ] A processor used for controlling physical systems like automobile engines. - [ ] A processor that runs sophisticated electronic devices like wireless routers.

Mini-lecture#

See this whiteboard.

Processor#

Processor categories based on flexibility#

Hierarchy in a complex processor#

Conventional processor#

Processor categories based on their role#

Two basic computer architectures#

Fetch-execute cycle#

Instructions#

Solution for the introductory problem#

  1. The inputs and outputs will be based on the ports of the described FIFO and flash interfaces. For example, mp_read_enable, mp_data, fl_address, fl_write_enable will be an output, input, output, output of our FPGA design, respectively.

  2. This problem could be solved by a state machine with the following states: read_address, read_length, read_payload, write_flash. The design would be a non-programmable logic processor, because it does not store any program that is executed at every clock cycle.

  3. Our design is non-programmable and fixed.

Note

We discuss here a very simplified interface for didactic purposes. In our example, the microprocessor does not read any data, so a FIFO for packets sent by the FPGA is unnecessary. However a more practical implementation will very likely contain a second FIFO for sending at least acknowledge packets back to the microprocessor.

Moreover, the link between the microprocessor and the FPGA probably requires a protocol controller (e.g., UART, CAN, SpaceWire for dealing with the physical (if applicable) and link-layer of the link.

Homework#

Exercises 4.1, 4.3, 4.4, 4.5 from the end of the chapter in the reading.